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STM32U545NE产品参数_符号图_现货专卖

作者： IC先生来源：网络浏览量：51 时间：2023-12-21 17:32:38

概述

STM32U545xx器件属于基于高性能Arm的超低功耗微控制器系列(STM32U5系列)

皮质

-M33 32位RISC内核。

大脑皮层

-M33内核具有单精度FPU(浮点单元)，支持所有Arm

单精度数据处理指令和所有数据类型。

大脑皮层

-M33核心还实现了一整套DSP(数字信号处理)指令和MPU(内存保护单元)，增强了应用程序的安全性。

这些器件嵌入高速存储器(512千字节闪存和274千字节SRAM)，一个Octo-SPI闪存接口，一个广泛的增强型I/ o，外设连接到三个APB总线，三个AHB总线和一个32位多AHB总线矩阵。

设备提供符合Arm TBSA (trusted-based security architecture)要求的安全基础

．

该器件具有嵌入式闪存和SRAM的几种保护机制:读出保护，写保护，安全和隐藏保护区域。

这些设备嵌入了几个增强安全性的外设:一个快速AES协处理器，一个具有抗DPA能力的安全AES协处理器和一个可以由具有快速AES的硬件共享的硬件唯一密钥，一个具有抗DPA能力的PKA(公钥加速器)，一个用于Octo-SPI外部存储器的动态解密引擎，一个HASH硬件加速器和一个真正的随机数生成器。

该设备提供主动篡改检测和保护，防止瞬态和环境扰动攻击，这要归功于几个内部监控，在攻击发生时生成秘密数据擦除。

这些器件提供一个快速14位ADC (2.5 Msps)，一个12位ADC (2.5 Msps)，一个比较器，一个运算放大器，两个DAC通道，一个内部电压参考缓冲器，一个低功耗RTC，四个32位通用定时器，两个16位PWM定时器专用于电机控制，三个16位通用定时器，两个16位基本定时器和四个16位低功耗定时器。

该器件支持MDF(多功能数字滤波器)，带有两个专用于连接外部sigma-delta调制器的滤波器。

这些设备还具有标准和先进的通信接口，如

c、3个spi、2个USARTs、2个UARTs、1个低功耗UART、1个SAI、1个数码相机接口(DCMI)、1个SDMMC、1个FDCAN、1个支持全速的USB主机和设备、1个通用同步8 /16位PSSI(并行数据输入/输出从接口)。

器件工作温度范围为-40 ~ +85℃(+105℃结)和-40 ~ +125℃(+130℃结)，电源电压范围为1.71 ~ 3.6 V。

一套全面的节能模式允许低功耗应用的设计。

支持一些独立电源，如ADC、dac、opamp和比较器的模拟独立电源输入，USB的3.3 V专用电源输入和最多14个I/ o，可独立供电至1.08 V。

这些设备提供8种封装，从48到100个引脚不等。

STM32U545NE符号图

STM32U545NE

STM32U545NE功能参数

Includes ST state-of-the-art patented technology
Ultra-low-power with FlexPowerControl
- 1.71 V to 3.6 V power supply
- –40 °C to +85/125 °C temperature range
- Low-power background-autonomous mode (LPBAM): autonomous peripherals with DMA, functional down to Stop 2 mode
- V_BAT mode: supply for RTC, 32 x 32-bit backup registers and 2-Kbyte backup SRAM
- 90 nA Shutdown mode (23 wake-up pins)
- 200 nA Standby mode (23 wake-up pins)
- 370 nA Standby mode with RTC
- 1.4 μA Stop 3 mode with 16-Kbyte SRAM
- 2.2 µA Stop 3 mode with full SRAM
- 3.0 µA Stop 2 mode with 16-Kbyte SRAM
- 4.6 µA Stop 2 mode with full SRAM
- 16.3 μA/MHz Run mode @ 3.3 V
内核
- Arm^® 32-bit Cortex^®-M33 CPU with TrustZone^®, MPU, DSP, and FPU
ART Accelerator
- 8-Kbyte instruction cache allowing 0-wait-state execution from flash and external memories: up to 160 MHz, 240 DMIPS
- 4-Kbyte data cache for external memories
Power management
- Embedded regulator (LDO) and SMPSstep-down converter supporting switchon-the-fly and voltage scaling
Benchmarks
- 1.5 DMIPS/MHz (Drystone 2.1)
- 651 CoreMark^® (4.07 CoreMark^®/MHz)
- 464 ULPMark™-CP
- 125 ULPMark™-PP
- 54 ULPMark™-CM
- 137000 SecureMark™-TLS
Memories
- 512-Kbyte flash memory with ECC, 2 banks read-while-write, and 100 kcycles
- 274-Kbyte SRAM including up to 64-Kbyte SRAM with ECC ON
- 1 Octo-SPI memory interface
Security and cryptography
- SESIP3 and PSA Level 3 Certified Assurance Target
- Arm^® TrustZone^® and securable I/Os, memories and peripherals
- Flexible life cycle scheme with RDP and password protected debug
- Root of trust thanks to unique boot entry and secure hide protection area (HDP)
- Secure firmware installation (SFI) thanks to embedded root-secure services (RSS)
- Secure data storage with hardware-unique key (HUK)
- Secure firmware upgrade support with TF-M
- 2 AES coprocessors including one withDPA resistance
- Public key accelerator, DPA resistant
- On-the-fly decryption of Octo-SPI external memories
- HASH hardware accelerator
- True random number generator, NIST SP800-90B compliant
- 96-bit unique ID
- 512-byte OTP (one-time programmable)
- Active tampers
Clock management
- 4 to 50 MHz crystal oscillator
- 32 kHz crystal oscillator for RTC (LSE)
- Internal 16 MHz factory-trimmed RC (±1%)
- Internal low-power 32 kHz RC (±5%)
- 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by LSE (better than ±0.25% accuracy)
- Internal 48 MHz with clock recovery
- 3 PLLs for system clock, USB, audio, ADC
General-purpose input/outputs
- Up to 82 fast I/Os with interrupt capability most 5V-tolerant and up to 14 I/Os with independent supply down to 1.08 V

Up to 17 timers and 2 watchdogs
- 2 16-bit advanced motor-control, 4 32-bit, 5 16-bit, 4 low-power 16-bit (available in Stop mode), 2 SysTick timers and 2 watchdogs
- RTC with hardware calendar and calibration
Up to 19 communication peripherals
- 1 USB full-speed selectable host or device controller
- 1 SAI (serial-audio interface)
- 4 I2C FM+(1 Mbit/s), SMBus/PMBus^®
- 5 USARTs (ISO 7816, LIN, IrDA, modem)
- 3 SPIs (4x SPIs with OCTOSPI)
- 1 CAN FD controller
- 1 SDMMC interface
- 1 multi-function digital filter (2 filters) + 1 audio digital filter with sound-activity detection
- Parallel synchronous slave interface
16- and 4-channel DMA controllers, functional in Stop mode
Graphic features
- 1 digital camera interface
Mathematical co-processor
- CORDIC for trigonometric functions acceleration
- Filter mathematical accelerator (FMAC)
Up to 20 capacitive sensing channels
- Support touch key, linear and rotary touch sensors
Rich analog peripherals (independent supply)
- 14-bit ADC 2.5-Msps with hardware oversampling
- 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode
- 2 12-bit DAC, low-power sample and hold
- 1 operational amplifier with built-in PGA
- 1 ultra-low-power comparator
CRC calculation unit
Debug
- Development support: serial-wire debug (SWD), JTAG, Embedded Trace Macrocell™ (ETM)