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STM32MP135A中文参数_符号图_原装销售

作者： IC先生来源：网络浏览量：30 时间：2023-12-22 11:20:59

概述

STM32MP135A/D器件基于高性能Arm

皮质

-A7 32位RISC内核，工作频率高达1ghz。

-A7处理器包括一个32kbyte的L1指令缓存，一个32kbyte的L1数据缓存和一个128kbyte的二级缓存。

-A7处理器是一款非常节能的应用处理器，旨在为高端可穿戴设备以及其他低功耗嵌入式和消费应用提供丰富的性能。

-A5，性能与Cortex相当

a9。

大脑皮层

-A7集成了高性能Cortex的所有功能

-A15和皮质

-A17处理器，包括硬件虚拟化支持、NEON™和128位AMBA

4 . axis总线接口。

STM32MP135A/D器件提供外部SDRAM接口，支持高达8gbit (1gbyte)密度的外部存储器，16位LPDDR2/LPDDR3或DDR3/DDR3L高达533mhz。

STM32MP135A/D器件采用高速嵌入式存储器，具有168 kb的内部SRAM(包括128 kb的AXI SYSRAM，两组8 kb和一组16 kb的安全AHB SRAM，以及8 kb的备份域SRAM)，以及广泛的增强型I/ o和连接到APB总线的外设，AHB总线和64位多层AXI互连，支持内部和外部存储器访问。

所有器件都提供两个adc，一个低功耗安全RTC，十个通用16位定时器，两个32位定时器，两个用于电机控制的PWM定时器，五个低功耗定时器，一个安全真随机数发生器(RNG)。

STM32MP135A符号图

STM32MP135A

STM32MP135A功能参数

Includes ST state-of-the-art patented technology
内核
- 32-bit Arm^® Cortex^®-A7
  - L1 32-Kbyte I / 32-Kbyte D
  - 128-Kbyte unified level 2 cache
  - Arm^® NEON™ and Arm^® TrustZone^®
Memories
- External DDR memory up to 1 Gbyte
  - up to LPDDR2/LPDDR3-1066 16-bit
  - up to DDR3/DDR3L-1066 16-bit
- 168 Kbytes of internal SRAM: 128 Kbytes of AXI SYSRAM + 32 Kbytes of AHB SRAM and 8 Kbytes of SRAM in Backup domain
- Dual Quad-SPI memory interface
- Flexible external memory controller with up to 16-bit data bus: parallel interface to connect external ICs and SLC NAND memories with up to 8-bit ECC
Security/safety
- TrustZone^® peripherals, 12 x tamper pins including 5 x active tampers
- Temperature, voltage, frequency and 32 kHz monitoring
Reset and power management
- 1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os)
- POR, PDR, PVD and BOR
- On-chip LDOs (USB 1.8 V, 1.1 V)
- Backup regulator (~0.9 V)
- Internal temperature sensors
- Low-power modes: Sleep, Stop, LPLV-Stop, LPLVStop2 and Standby
- DDR retention in Standby mode
- Controls for PMIC companion chip
Clock management
- Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz LSI oscillator
- External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator
- 4 × PLLs with fractional mode
General-purpose input/outputs
- Up to 135 secure I/O ports with interrupt capability
- Up to 6 wakeup
Interconnect matrix
- 2 bus matrices
  - 64-bit Arm^® AMBA^® AXI interconnect, up to 266 MHz
  - 32-bit Arm^® AMBA^® AHB interconnect, up to 209 MHz
4 DMA controllers to unload the CPU
- 56 physical channels in total
- 1 x high-speed general-purpose master direct memory access controller (MDMA)
- 3 × dual-port DMAs with FIFO and request router capabilities for optimal peripheral management

Up to 30 communication peripherals
- 5 × I²C FM+ (1 Mbit/s, SMBus/PMBus™)
- 4 x UART + 4 x USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave)
- 5 × SPI (50 Mbit/s, including 4 with full-duplex I²S audio class accuracy via internal audio PLL or external clock)
- 2 × SAI (stereo audio: I²S, PDM, SPDIF Tx)
- SPDIF Rx with 4 inputs
- 2 × SDMMC up to 8 bits (SD/e•MMC™/SDIO)
- 2 × CAN controllers supporting CAN FD protocol
- 2 × USB 2.0 high-speed Host
  - or 1 × USB 2.0 high-speed Host+ 1 × USB 2.0 high-speed OTG simultaneously
- 2 x Ethernet MAC/GMAC
  - IEEE 1588v2 hardware, MII/RMII/RGMII
- 8- to 16-bit camera interface, 3 Mpix @30 fps or 5Mpix @15 fps in color or monochrome with pixel clock @120 MHz (max freq)
6 analog peripherals
- 2 × ADCs with 12-bit max. resolution up to 5 Msps
- 1 x temperature sensor
- 1 x digital filter for sigma-delta modulator (DFSDM) with 4 channels and 2 filters
- Internal or external ADC reference V_REF+
Graphics
- LCD-TFT controller, up to 24-bit // RGB888
  - up to WXGA (1366 × 768) @60 fps or up to Full HD (1920 x 1080) @ 30 fps
  - pixel clock up to 90 MHz
  - two layers (incl. 1 secured) with programmable color LUT
Up to 24 timers and 2 watchdogs
- 2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
- 2 × 16-bit advanced timers
- 10 × 16-bit general-purpose timers (including 2 basic timers without PWM)
- 5 × 16-bit low-power timers
- Secure RTC with sub-second accuracy and hardware calendar
- 4 Cortex^®-A7 system timers (secure, nonsecure, virtual, hypervisor)
- 2 × independent watchdogs
Hardware acceleration
- ECDSA verification with SCA
- HASH (SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-3), HMAC
- 1 x true random number generator (6 triple oscillators)
- 1 x CRC calculation unit
Debug mode
- Arm^® CoreSight™ trace and debug: SWD and JTAG interfaces usable as GPIOs
- 4-Kbyte embedded trace buffer
3072-bit fuses including 96-bit unique ID, up to 1280 bits available for user
All packages are ECOPACK2 compliant